VHDL1602时钟.doc

VHDL1602时钟VHDL1602时钟VHDL1602时钟VHDL1602液晶显示时钟驱动代码libraryIEEE;useIEEE。STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH。ALL;useIEEE.STD_LOGIC_UNSIGNED。ALL；entitylec1602isPort（CLK：instd_logic；LCD_RS：outstd_logic;LCD_RW:outstd_logic；LCD_EN:outstd_logic;LCD_Data：outstd_logic_vector（7downto0）)；endlec1602；architectureBehavioraloflec1602issignalcount1:std_logic_vector(15downto0）；signalclk1，clk2：std_logic;signalge1,shi1,bai1，qian1：integerrange0to10；signalge2,shi2，bai2,qian2：integerrange0to6;signalg,s,b,q,w,qww:std_logic;typeram1isarray（0to9）ofstd_logic_vector(7downto0)；constantcgram1:ram1:=(x”30”,x"31",x"32"，x"33”,x"34”，x”35”,x"36"，x"37”，x"38”，x"39")；typestateis（set_dlnf，set_cursor，set_dcb,set_cgram，write_cgram,set_ddram);signalcs：state：=set_dlnf;begink1:process（clk）variablecount:integerrange0to100000;beginifclk’eventandclk='1’thencount1<=count1+1;ifcount<=50000thenclk1〈=’0'；count：=count+1;elsifcount〉50000andcount<=100000thenclk1<=’1’；count：=count+1；elsecount：=0;endif;endif;endprocessk1；LCD_RW〈=’0’;LCD_EN<=clk1；k2：process（clk1）variablecount2:integerrange0to500；beginif（clk1’eventandclk1='1'）thenif（count2<=250）thenclk2〈=’0';count2:=count2+1;elsifcount2〉250andcount2<=500thenclk2<='1';count2：=count2+1;elsecount2:=0;endif;endif;endprocessk2；k3:process（clk2)beginif(clk2’eventandclk2='1'）thenif(ge1=9）thenge1〈=0；g<=’1’;elsege1〈=ge1+1；g<=’0'；endif;endif；endprocess;k4:process（g）beginif（g’eventandg='1')thenif（ge2=5）thenge2〈=0;s〈='1’；elsege2<=ge2+1;s<='0’；endif；endif;endprocess；k5:process（s)beginif（s'eventands=’1’）thenif(bai1=9）thenbai1<=0；q<='1'；elsebai1<=bai1+1;q〈='0’；endif；endif;endprocess;k6：process（q）beginif（q'eventandq='1')thenif（bai2=5)thenbai2〈=0；w<='1’；elsebai2〈=bai2+1;w〈=’0';endif;endif；endprocess;k16:process（w）beginif（w'eventandw=’1’）thenif（qian1=9）thenqian1〈=0；qww<=’1'；elseqian1〈=qian1+1；qww<=’0’；endif；endif；endprocess;k66：process（qww)beginif(qww’eventandqww='1')thenif(qian2=1）thenqian2〈=0;elseqian2〈=qian2+1;endif;endif;endprocess；process(clk1，cs)variablecnt：std_logic_vector（3downt