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基于FPGA的LDPC码译码器的实现
1.Introduction
Low-densityparity-check(LDPC)codesareamongthebesterror-correctingcodesinusetoday.Theyareusedinmanyapplications,suchaswirelesscommunication,digitalbroadcasting,andopticalcommunication.LDPCcodescanachievenear-Shannon-limitperformancewithlowencodinganddecodingcomplexity.Duetotheirhighperformanceandlowcomplexity,theyhavebecomeapopularchoiceformoderncommunicationsystems.Inthispaper,wewilldiscusstheimplementationofanLDPCcodedecoderonafield-programmablegatearray(FPGA).
2.Background
LDPCcodesarelinearblockcodes,whichmeansthattheoutputcodeisalinearcombinationoftheinputcode.Theyaredefinedbyaparity-checkmatrixH,whichspecifiestheconstraintsonthecode.ThecodeistransmittedbymultiplyingtheinputmessagewithageneratormatrixG,resultinginacodeword.Thedecoderattemptstorecovertheoriginalmessagefromthereceivedcodeword.
LDPCdecodingisaniterativeprocessthatinvolvescomputingtheprobabilitiesofallthepossiblevaluesofthebitsinthemessageandthenupdatingtheseprobabilitiesbasedonthereceivedcodeword.Theprocesscontinuesuntilamaximum-likelihoodestimateisreached.Thecomplexityofthisprocessdependsonthesizeoftheparity-checkmatrix,whichdeterminesthenumberofiterationsrequiredtoachievethemaximumlikelihoodestimate.
3.LDPCDecoderArchitecture
ThearchitectureofanLDPCdecodercanbedividedintothreemainblocks:thechecknodeprocessingblock,thevariablenodeprocessingblock,andthecontrolblock.
Thechecknodeprocessingblockcomputesthechecknodevaluesbasedontheincomingvariablenodevalues.Eachchecknodereceivesmultiplevariablenodevaluesandusesthemtocalculateanewchecknodevalue.Thechecknodevaluesarebroadcastedbacktoalltheconnectedvariablenodes.
Thevariablenodeprocessingblockcomputesthevariablenodevaluesbasedontheincomingchecknodevalues.Eachvariablenodereceivesmultiplechecknodevaluesandusesthemtocalculateanewvariablenodevalue.Thevariablenodevaluesarebroadcastedbacktoalltheconnectedchecknodes.
Thecontrolblockmanagestheoveralldecodingprocess.Itinitializesthevariablenodevalues,startstheiterativedecodingpro