多功能数字钟课程设计整点报时与闹钟功能VHDL代码.docx

多功能数字钟课程设计整点报时与闹钟功能VHDL代码

第一篇：多功能数字钟课程设计整点报时与闹钟功能VHDL代码libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;--Uncommentthefollowinglinestousethedeclarationsthatare--providedforinstantiatingXilinxprimitivecomponents.--libraryUNISIM;--useUNISIM.VComponents.all;entitytimkeeperisPort(up,setpin,upclk,settime,run:instd_logic;a0,a1,b0,b1,c0,c1:outstd_logic_vector(3downto0);result:outstd_logic);endtimkeeper;architectureBehavioraloftimkeeperiscomponenth_m_s_timeport（clk0,clk1,ce:instd_logic;sec0,sec1:bufferstd_logic_vector(3downto0);lock:instd_logic_vector(2downto0);up:instd_logic;min0,min1:bufferstd_logic_vector(3downto0);hour0,hour1:bufferstd_logic_vector(3downto0);ov:outstd_logic);endcomponent;componentdateport（clk0,clk1,ce:instd_logic;lock:instd_logic_vector(2downto0);up:instd_logic;mon0,mon1,year0,year1:instd_logic_vector(3downto0);date0,date1:bufferstd_logic_vector(3downto0);ov:outstd_logic);endcomponent;componentmonth_yearport（clk0,clk1,ce:instd_logic;lock:instd_logic_vector(2downto0);up:instd_logic;mon0,mon1:bufferstd_logic_vector(3downto0);year0,year1:bufferstd_logic_vector(3downto0));endcomponent;componentLED_dispport（lock:instd_logic_vector(2downto0);sec0,sec1,min0,min1,hour0,hour1:instd_logic_vector(3downto0);date0,date1,mon0,mon1,year0,year1:instd_logic_vector(3downto0);a0,a1,b0,b1,c0,c1:outstd_logic_vector(3downto0));endcomponent;componentalarmPort（hour1,hour0,min1,min0,sec1,sec0:instd_logic_vector(3downto0);settime,run:instd_logic;result:outstd_logic);endcomponent;signalTlock:std_logic_vector(2downto0);signalTsecond_wave:std_logic;signalTsec0,Tsec1,Tmin0,Tmin1,Thour0,Thour1:std_logic_vector(3downto0);signalTdate0,Tdate1,Tmon0,Tmon1,Tyear0,Tyear1:std_logic_vector(3downto0);signalTovday,Tovmonth:std_logic;signalvcc:std_logic;beginvccifrising_edge(setpin)thenTlockendif;endprocess;u2:h_m_s_timeportmap(Tsecond_wave,upclk,vcc,Tsec0,Tsec1,Tlock,up，Tmin0,Tmin1,Thour0,Thour1,Tovday);u3:dateportmap(Tovday,upclk,vcc,Tlock,up,